Automated Sneak Circuit and Design Concern Analysis on the Personal Computer
An Informational Report
Phase Three Logic
HomePage: http://www.Phase3.com
December 2016
Tom Williams, Applications Engineer
Farhad Manteghi, Software Engineer
Charles Neal, Director, Engineering
Dr. Chong Lee, President
TABLE OF CONTENTS
(click on Chapter text to jump to that section)
TRADITIONAL SNEAK CIRCUIT ANALYSIS
STEPS TO PERFORMING A SNEAK CIRCUIT ANALYSIS WITH CAPFAST/SCAT
List of Illustrations
(The illustrations listed below are in the main body of this paper and are not linked from here. Please browse through the paper to see them)
Figure 1: Five topological patterns associated with sneak circuits (Sohar, 1994)
Figure 2: (a) Motor symbol drawn in CapFast, and (b). the attributes assigned to it
Figure 3: Power window circuit
Figure 4: Power window circuit with added emergency power switch
Figure 5: Session log for a sneak circuit analysis of power window circuit
Figure 6: First undesirable path revealed by sneak circuit analysis
Figure 7: Second undesirable path revealed by sneak circuit analysis
Figure 8: First undesirable path after insertion of diode
Figure 9: Second undesirable path after insertion of diode
Figure 10: Undesirable path after insertion of 2 additional diodes
Figure 11: Emergency power switch plus 4 Diodes
Abstract
Sneak Circuit Analysis may now be carried out effectively on a personal computer using the Windows-based software package, CapFast/SCAT. The product provides a complete environment for design entry and sneak circuit analysis, as well as an expert system for addressing the design concerns defined in Appendix C of MIL-STD-1543B. Users of other EDA systems such as Mentor Graphics and Cadence, may use an additional utility program to convert their schematics and symbols to the required format for CapFast/SCAT. This report provides an overview of the salient features of the product, including an example of its use as a design checker.
Acknowledgment
The methodology and implementation of sneak circuit analysis techniques described herein were funded by and developed in cooperation with USAF Rome Laboratories, under project engineers Bruce Dudley and Ed DePalma.
Introduction
Defective designs in the aerospace industry can end in spectacular failures and loss of life, but when they occur in other industries, we often hear about them only because of the large costs of a product recall. For example, a car radio containing a circuit, which under certain operating conditions produced a short circuit that melted insulation and created a fire hazard, was the object of an automobile recall not long ago. Similar scenarios can be imagined for almost any electric appliance, and the simplest remedy in many cases consists of throwing the item away. The manufacturer must commit to making thousands of items at a time, however, so the stakes are much higher for even the relatively minor design flaws that tarnish a product’s image, even if they pose no hazard.
Most engineers, thus, would love to see the evolution of desktop reliability tools shift out of low gear. Unfortunately, the complex, labor-intensive methods traditionally required to perform such analyses continue to hobble growth in the number of specialists qualified to do the job. So, reliability assurance tasks end up being subcontracted to a handful of high-priced specialty houses, and a company’s design engineers don’t get much of a chance to learn the process. No wonder many engineering decision-makers put off committing financial resources to the development of reliability capabilities in their own businesses until they can bring a complete expert system software package in-house.
They may be in for a long wait as far as a sneak circuit capability is concerned. Automated approaches have been in development for over 25 years now (Carpignano & Poucet, 1994), and still require oversight by a designer experienced in the technique. Very likely, the hallmark of an expert analysis, generated with the best tools, will remain the sum total of experience in the technique brought to bear by the expert orchestrating the sneak studies.
An alternative approach aims at bringing the capability aboard immediately; company engineers will be encouraged to apply it to their designs before sending them to the outside experts. According to this view, knowledge of the technique can grow through the process of comparing inside analyses with those of the outside experts, until designers become experienced enough to begin incorporating their own sneak circuit analyses as a new step in their own design processes. Suggestions to this effect from clients motivated a joint effort by SoHaR and Phase Three Logic to collaborate in producing such software at a low enough price to attract the interest of companies weighing the possibilities in a ‘bootstrap’ approach. While a workstation-based sneak circuit analytical capability has been in the making for 25 years or so, spearheaded by the aerospace industry (SoHaR, 1994), the goal of the two company’s efforts has aimed to capitalize on the speed and memory capabilities of recent model personal computers. The sheer processing power now available has narrowed the gap with workstations and has made possible the implementation of SoHaR’s proprietary methodology on the PC platform.
Traditional Sneak Circuit Analysis (SCA)
Sneak circuit analysis is a method for identifying signal paths in electrical designs that may cause an unwanted event to occur, or conversely, prevent a desired event from occurring. The term specifically excludes component failure, which is not under the designer’s control. Also excluded are errors in the logic implemented in chips that produce the wrong logic levels on their outputs. What SCAT does, is encompass all power flow paths arising from the synergy between possible courses of action of an operator, and the interconnection of components, and at higher levels, systems (O’Connor, 1985). Designers, as a rule, are pretty good at anticipating the effects of errors of omission; the failure to operate a switch, say, or detect an alarm condition. A greater challenge arises in trying to anticipate the effects of incorrect actions taken by an operator (Hahn, Blackman, and Gertman, 1991), which can cause any number of external asynchronous inputs that are NOT under the control of the designer. For example, imagine any situation where children are apt to be operators of the system or device, and the possibilities for illogical control switching sequences become apparent.
Historically, knowledge of sneak circuits grew out of experience; evolving into a collection of topological patterns most often associated with their occurrence (SoHaR, 1994). Figure 1 illustrates the five basic patterns that have come to be recognized as producing the vast majority of sneak paths. They are quite simple, viewed in isolation, but finding them in complex schematics can be a daunting task, as present analytic methods attest. Typically, large schematics must first be converted to a network tree representation, as a means of eliminating unnecessary and distracting detail while preserving the essential features of circuit operation. The network trees then must be investigated for matching topological patterns, an endeavor prone to error if the analyst is imprecise and/or unsystematic. For each pattern, lengthy ‘clue lists’ must be studied to pinpoint sneak circuit conditions. Automation of this process has focused on the creation of the network trees by various methods of data partitioning and encoding, but pattern recognition by an analyst was and still is required.
SoHaR’s Approach
SoHar’s engineers, recognizing that the majority of sneak paths come from the ‘H’ pattern, began by developing an algorithm for locating them. Modification of this algorithm then resulted in an approach to systematically identify the remaining four topological patterns associated with sneak paths. The ‘H’ pattern identification algorithm is as follows: First, all possible signal paths from a chosen source node(s) to one or more sink nodes are located and tabulated. Next, those paths that collectively allow bi-directional current flow in one or more components in the path are identified, and these represent the ‘H’ pattern sneak paths. A computationally intense, but very simple idea, this algorithm depends entirely on the “brute force” of the computer to systematically track down every possible path between the selected nodes for any possible setting of the switching elements. Neither network trees nor pattern recognition figure into the computations, rather the consistency, speed, and tireless accuracy of the computer are the most important considerations. SoHaR’s method of tabulating the data remains proprietary, but the method depends on the raw data obtained from CapFast by way of Phase Three Logic’s CapFast EDIF writer program.
Figure 1: Five topological patterns associated with sneak circuits (Sohar, 1994)
Configuration of CapFast/SCAT
Three software tools comprise the package: For sneak circuit and other analyses, SoHaR contributed its Windows-based Sneak Circuit Analysis Tool (SCAT) software. A second package, CapFast, by Phase Three Logic, provides the graphical schematic interface for user input of design data. The third package consists of Phase Three Logic’s EDIF writer utility, SCH2EDIF, for generating an EDIF netlist from the graphics oriented CapFast design data base. SCAT works entirely at the netlist level until ready to display results. If sneak paths are found, they are listed textually, and may also be viewed on the schematic under study. The results of design concerns analyses get displayed as a written test record. A hard copy of all processing steps and test results may be printed out at any time, and analyses may be interrupted and saved for later completion.
Down to Basics
CapFast has been a commercial product for a long time, emerging from the nascent CAE world in 1984. Like all schematic capture tools, it provides a drawing easel for creating or placing logical entities called symbols, whose inputs and outputs (ports) are interconnected by lines (wires). Wires and symbols may be assigned attributes which apply to just a single instance, or generically to all symbols of the same type. CapFast includes a large library of predefined symbols coinciding with standard industry parts, as well as a symbol editor for creating new ones. Typically, the symbol editor is used to create a symbol representation of an entire schematic, which may in turn be used as an element in a higher level schematic (Stettler, 1994). The construction and use of these custom hierarchical symbols may be taken to any number of levels of functionality.
How a design tool stores and manages the database evolved from these basic ideas affects the precision and ease with which other analytical tools can access it. The ability of the designer to spot check or modify it can also be affected. CapFast keeps its database in a completely open ASCII format that allows modification with any text editor. Variations of the ASCII format are widely used by other CAE tools requiring schematic design data as input, and CapFast provides translators for converting its database to many other formats, such as EDIF 200, which has become a widely used de-facto standard for electronic data interchange (Phase Three Logic, 1991 #1).
Creating a CapFast Design
Hierarchical designs are generally easier to create and understand than multi-page flat designs. Schematic editors, on the other hand, enforce no set approach, and CapFast handles arbitrarily large designs of either type (Phase Three Logic, 1991 #2). It is useful to walk through the layout of a small schematic to illustrate how CapFast works. The design was taken from the specifications for the power window circuit of a recent model sedan and consists primarily of switches for routing power to the window servo motors. The lack of emergency power stands out as a weakness in many such designs. Here CapFast will be used to put together the circuit as the manufacturer originally designed it. Then we will add a source of emergency power and utilize the sneak circuit capability of SCAT to double check the enhancement.
CapFast’s standard library contains most of the analog parts required. So to start, the schematic editor is invoked. Its main window conforms to the Microsoft Windows standard: a menu bar across the top of the main activity area, and a small command and message area at the bottom. The menu bar lists the top-level selections recognized by the editor. Commands may be executed in a variety of ways: With the mouse, by typing the key corresponding to the underlined letter in the name of a menu selection, or a combination of the two. Schematic editors distinguish themselves in a large sense by the efficiency (speed) with which users may move between commands. The greatest speed in many Windows based programs, including CapFast, comes from using the mouse and keyboard together.
After the initial setup, like setting the drawing scale, configuring the library, and placing a border, parts are selected and placed in the drawing area of the main window. An experienced user can place and nterconnect parts very rapidly using mouse and keyboard combinations. Before the design can be finished, a symbol for the dc servo motor must be created and made available to the schematic editor. So, after placing every symbol except the motor, we save the present incomplete drawing, minimize the schematic window, and invoke the symbol editor.
Figure 2: (a) Motor symbol drawn in CapFast, and (b). the attributes assigned to it
The motor symbol to be created could hardly be simpler, but offers a perfect illustration of how CapFast associates electrical characteristics and specifications with the graphical images utilized in drawings. Symbols consist of an image with attached ports. The graphic may be quite elaborate and even include text, but the ports are the only elements of it that carry electrical meaning into the schematic editor. The creation of the motor symbol is begun by drawing a graphic image for it; something that provides a good visual mnemonic. Two bi-directional ports are added last to complete the picture (Figure 2a). Additional symbol attributes, called properties, along with their values, may be entered in a properties list that accompanies every CapFast symbol. The standard CapFast properties, found in the predefined library, mesh well with many simulation and layout tools, as they cover most of the electrical and physical specifications the downstream tools require. Four of the standard properties are chosen, to further describe the motor symbol (Figure 2b), but any number of properties may be defined, and the capability exists to define entirely original properties.
Figure 3: Power window circuit
Mainly composed of switches, the completed design represents the circuit which controls one of the vehicle’s four power windows (Figure 3). Four such modules connected in parallel comprise the entire window circuit. The car’s ignition switch must be on to activate the main power relay that energizes the circuit. Each window may be controlled from the master switch bank on the driver’s door or from its passenger switch by the window. The schematic does not reflect the obvious thought that went into the physical shape of the switches and their layout on the doors to minimize the chances of a hazardous operating condition. For instance, the windows will not work unless the ignition key is in and turned a notch, a requirement that ensures the presence of a driver before the windows will operate. Children left alone in the car cannot play with the windows and accidentally close one on a finger, or worse. The driver also has the option of killing power to the window circuit (and all systems) if an emergency occurs in which arcing or sparking could cause a fire. And a window cannot accidentally be raised if an object falls against the switches on the driver’s arm rest. As safe as the design appears, a scenario in which the occupants must escape the vehicle through the windows during a power failure or shut-down, has not been allowed for. Someone once called this the ‘tire iron’ scenario, the name he coined after developing his own expedient for getting out of the car if the doors are jammed and the windows won’t open.
Figure 4: Power window circuit with added emergency power switch
Suppose it becomes desirable to make emergency power available to operate the windows. This can easily be done by adding the emergency switch shown in Figure 4, which could be located in an easily accessible location for the driver, and yet inaccessible to children in order to prevent the windows being operated without the driver present. A sneak circuit analysis will now be run on the revised design to gain additional insight into the effects of the modification.
Steps to performing a sneak circuit analysis with CapFast/SCAT
To prepare for a sneak circuit analysis, behavioral models are created for each of the components in the design. How each device responds to the flow of power in the circuit, and its role in the transfer of power are the main concerns. Sneak circuit analysis reveals possible routes by which loads may be energized, so the kind of circuitry susceptible to sneak paths is typically analog power switching and distribution circuitry. Digital circuitry, by contrast, usually does not produce power flow. (It consumes power, but only in small amounts as a byproduct of its inherent function of producing logic signals having very low power content. Failures of digital circuitry are usually the result of logic failures, not power failure). The models files used by SCAT have a simple ASCII format, and can be edited with any text editor. They list, for each component, the polarity of power flow from one port to another within the component. For example, in the excerpt shown below, the model entry for the diode specifies unidirectional flow from port N+ to port N-. The model entry for the relay specifies unrestricted flow in either direction between its switch ports (S1 and S2), and similar bi-directional power flow between the ports (C1 and C2) of its coil. The single-pole double-throw switch calls for similar bi-directional flow between its ports X2 and X1, ports X2 and X3, and, if it is a ‘make-before-break’ type (a designation that may be specified when setting up other parameters of the analysis), ports X1 and X3.
N+,N-
DIODE ; model for CapFast symbol
S1,,S2
C2,,C1
RELAY1 ; model for CapFast symbol
X2,,X1
X2,,X3
/M
X1,,X3
SPDT ; model for CapFast symbol
SCAT model preparation ought to be a careful, unhurried activity because ultimately, the quality of the end results depends on the precision of the models. Also, models added to the models files become library references for future designs that incorporate the underlying part. After the models have been added to the models files, the SCAT software may be started, which leads the user through a simple series of pre-processing activities which culminate in the execution of the actual sneak circuit analysis. The software maintains a detailed log of the processing steps and their results, which may be printed out or incorporated in word-processing documents to establish a permanent written record. Such an audit trail has become an important requirement of sneak circuit analyses conducted under government contract. The pre-processor checks that the symbol files underlying the graphical elements used in the schematic are available to the program. It then invokes the CapFast EDIF Writer to translate the schematic into an EDIF netlist. Next, the netlist is processed in order to extract the data that is relevant to the analysis. After that, the preprocessor obtains additional behavioral parameters from the designer, such as the combinations of power sources and sinks to be studied, the type of each switching device’s behavior (make-before-break or break-before-make) and how the designer chooses to model circuit capacitance.
Session Log for Project: FIG3T1
Creation Date: 11/17/95
Project Description: Power window circuit modified by addition of emergency switch.
Original Schematics Located In Directory: h:\scat.art\
Pre-Processed Schematics and Symbols:
Pre-processed schematic no. 1: h:\scat.art\fig3.sch
Pre-processed Symbol No. 1: h:\scat.art\relay1.sym
Pre-processed Symbol No. 2: h:\scat.art\res.sym
Pre-processed Symbol No. 3: h:\scat.art\gnd.sym
Pre-processed Symbol No. 4: h:\scat.art\sw.sym
Pre-processed Symbol No. 5: h:\scat.art\fuse.sym
Pre-processed Symbol No. 6: h:\scat.art\lboat.sym
Pre-processed Symbol No. 7: h:\scat.art\rboat.sym
Pre-processed Symbol No. 8: h:\scat.art\ba200tr.sym
Pre-processed Symbol No. 9: h:\scat.art\spdt.sym
Pre-processed Symbol No. 10: h:\scat.art\motor.sym
Netlist Generation
Source design used to generate netlist: h:\scat.art\fig3.dsn
Netlist generated: h:\scat3\program\fig3t1\fig3.net
Processed Netlist:
Netlist: h:\scat3\program\fig3t1\fig3.net
Detected Version: CapFast, EDIF 2.0.0
Sneak Circuit Analysis…Started
Start Date: 11/17/95
Start Time: 08:47:38
Iteration Number: 1
Source Node: +12VDC
Sink Node(s): GND, SNK
Bipath(1,1) = +12VDC, FIG3:S1, FIG3:SPDT#56, FIG3:MOTOR#68, FIG3:SPDT#55, FIG3:S3, FIG3:R1, GND
Bipath(2,2) = +12VDC, FIG3:S1, FIG3:SPDT#55, FIG3:MOTOR#68, FIG3:SPDT#56, FIG3:S2, FIG3:R1, GND
Bipath(3,4) = +12VDC, FIG3:S1, FIG3:S2, FIG3:SPDT#56, FIG3:MOTOR#68, FIG3:SPDT#55, FIG3:S3, FIG3:R1, GND Bipath(4,5) = +12VDC, FIG3:S1, FIG3:S3, FIG3:SPDT#55, FIG3:MOTOR#68, FIG3:SPDT#56, FIG3:S2, FIG3:R1, GND
Paths found in this iteratation: 5
Bipaths found in this iteratation: 4
Iteration Number: 2
Source Node: CB30AMP
Sink Node(s): GND, SNK
Bipath(1,1) = CB30AMP, FIG3:RLY1, FIG3:SPDT#56, FIG3:MOTOR#68, FIG3:SPDT#55, FIG3:S3, FIG3:R1, GND
Bipath(2,2) = CB30AMP, FIG3:RLY1, FIG3:SPDT#55, FIG3:MOTOR#68, FIG3:SPDT#56, FIG3:S2, FIG3:R1, GND
Bipath(3,4) = CB30AMP, FIG3:RLY1, FIG3:S2, FIG3:SPDT#56, FIG3:MOTOR#68, FIG3:SPDT#55, FIG3:S3, FIG3:R1, GND Bipath(4,5) = CB30AMP, FIG3:RLY1, FIG3:S3, FIG3:SPDT#55, FIG3:MOTOR#68, FIG3:SPDT#56, FIG3:S2, FIG3:R1, GND Paths found in this iteratation: 5
Bipaths found in this iteratation: 4
Iteration Number: 3
Source Node: GUAGE
Sink Node(s): GND, SNK
No Bipaths Found Paths found in this iteratation: 1
Bipaths found in this iteratation: 0
Sneak Circuit Analysis…Completed
Figure 5: Session log for a sneak circuit analysis of power window circuit
Figure 5 shows the log of the entire session for this sneak analysis of the power window circuit with the added emergency power source. The analysis turned up eight potential sneak paths: Four associated with the normal power source and four associated with our added emergency power switch. The analyst may now determine which of the potential sneak paths warrant a remedy. To gain the best possible intuitive insight into the meaning of the results revealed by the log, the software allows the user to highlight, in a bold color on the CapFast schematic, any individual sneak path he chooses. The four associated with normal power conditions can be eliminated as sources of concern since they do not energize any portions of the circuit we do not wish energized. Of the remaining four, two attract attention because they show that under emergency power conditions, loads other than the power windows receive emergency power (Figures 6 and 7). Assuming the driver may want to kill power to all electrical systems for safety’s sake, yet maintain window operation, the two sneak paths are deemed undesirable. Returning to CapFast, a diode may be inserted to remove them.
Figure 6: First undesirable path revealed by sneak circuit analysis
Figure 7: Second undesirable path revealed by sneak circuit analysis
A sneak circuit analysis performed on the new design (with the added diode) confirms that the two sneak conditions no longer exist. Having resolved the initial problem by adding a diode at the appropriate spot, two new highlighted signal paths from our second analysis indicate other loads can be energized during a power-down emergency if the driver and a passenger operate their respective window switches simultaneously. Figures 8 and 9 show the signal paths highlighted by CapFast/SCAT. After inserting two more diodes as a remedy, yet another analysis reveals that all sneak circuits to other loads have been eliminated in the modified design. Still, in viewing the signal paths in the circuit with the three added diodes (Figure 10), another improvement comes to mind. Recall that one of the reasons for a master ignition switch to energize the power window circuit was prevention of an injurious window closing by an unsupervised child. The emergency power switch, even if inaccessible, re-creates the problem of the window circuit accidentally being energized without a driver present. The new switch could be made totally inaccessible (except to the driver), but doing so would partly defeat its purpose. Anyway, common sense suggests power window injuries would happen almost entirely from accidental closings, so blocking emergency power to the passenger ‘UP’ switch with a diode inserted between the passenger switch power ports, offers a way to prevent the worst case scenario. Then, if children operate the emergency power switch and energize the windows, without a driver in the car the windows can only be lowered. A final sneak circuit analysis reveals that no problem signal paths remain after the fourth diode is added to the circuit, as shown in Figure 11.
Figure 8: First undesirable path after insertion of diode
Figure 9: Second undesirable path after insertion of diode
While admittedly simple, the power window circuit illustrates how the sneak circuit capability of CapFast/SCAT can be used, not only for the primary purpose for which it was developed, but also for focusing a designer’s attention on signal flow in a design. The analyses can be executed rapidly and repetitively, so circuit modifications can be tested efficiently at every step in the design process.
Figure 10: Undesirable path after insertion of 2 additional diodes
Figure 11: Emergency power switch plus 4 Diodes
Design Concerns Analysis
Besides its sneak circuit capability, CapFast /SCAT includes an interactive expert system for conducting design concerns analyses (DCA’s). This part of the software was built around the design concern rules listed in Appendix C of MIL-STD-1543B (SoHaR, 1994). The way it works is, a user selects any subset of the more than 40 rules of correct design practice, and the program then leads the user on a diagnostic exploration of his/her design, in search of violations. For each design concern, the program may ask the designer to answer one or more simple questions about the design under study. The answers, along with the data extracted from the design, are then matched heuristically against symptom lists developed by SoHar’s reliability engineers. Suggestions and critiques alert the user when a potential problem is detected.
The effectiveness of an expert system hinges, naturally, on the ability of the expert whose knowledge and experience are encoded in the software. Next in importance is the accuracy of the programming routines that attempt to replicate the expert’s thinking pattern. Certain individuals, working successfully in the field, develop support for this reason. For example, Steve Harbater parlayed his early pioneering work in sneak circuit analysis at The Boeing Company into a job developing the Computer-Aided Reliability Diagnostic System (CARDS) design rule checker used at General Dynamics (Harbater and Tonelli, 1990). Likewise, SoHaR has garnered a reputation as a premier reliability subcontractor. Unfortunately, competitive pressures make it difficult if not impossible to obtain more than sketchy details about product implementation, so integrity is perhaps the most important criterion for choosing a vendor in this area.
Conclusion
The reliability software package, CapFast/SCAT, can be utilized for disciplined reliability studies, or, more informally, to help the designer work by directing attention to circuit possibilities that may not have occurred to him/her. Since the processing speeds and storage capacities of personal computers are rapidly catching up to workstations, the old complaint that personal computers lack the capacities to run such complex software has all but evaporated. The CapFast/SCAT package handles design entry and modification, with a full-featured schematic capture interface that serves the dual purposes of design capture and graphical display of sneak circuits. To address the preference of some designers for workstation based design entry tools, translators are available to convert to and from the EDIF 200 format. Designs from almost any tool that can write its output to EDIF format can be utilized by the program, making sneak analyses possible on archived designs, and allowing multiple platform support by just one personal computer dedicated to sneak circuit analysis.
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